The invention relates to a system and method for measuring jitter in repetitive electrical signals, and more particularly, to measuring and quantitatively analyzing the jitter in clock signals using a tester to easily sort chips based on the jitter measurements, thereby eliminating the need for external instrumentation.
A phase-locked loop (PLL) is a component that is commonly used in many circuit designs. A circuit of this kind typically synchronizes an input signal to an output signal. It operates such that the output signal tracks the input signal in phase or relative position of the waveform. The frequency can be the same, or by means of a divider or multiplier circuit, the input and output frequency may differ while still being synchronized in-phase. Jitter of the output of the clock signal in a PLL determines the quality and even the performance of the output signal and of any circuit depending thereof. Therefore, jitter measurements in a PLL become indispensable for any circuit design. Such PLL circuits have proven to be excellent vehicles for determining the presence of jitter and lend themselves as vehicles for sorting good chips from bad ones.
It is well known that the semiconductor industry constantly strives to achieve higher processing speeds in connection with computers, telecommunication equipment, and the like. The common factor which extends to all the technological fields strives to achieve an ever increasing transfer of large volumes of data at high speed. By way of example, microprocessors move data at speeds which are based on high frequency clocks that determine the rate at which electrical signals are clocked through the circuitry.
FIG. 1 shows a basic block diagram of a PLL. An input signal and an oscillator (feedback) signal are fed to a phase detector. The input is the signal to be synchronized with, while the feedback from the voltage controlled oscillator (VCO) is the output signal to be synchronized with the input, provided the circuit operates correctly. The phase detector outputs a voltage through the loop filter that is proportional to the phase difference between the input and feedback waveforms. This proportional voltage is fed to the input of the VCO. The VCO frequency is controlled by the input voltage and its starting frequency approximates the input frequency of the phase detector. If the input and output are out-of-phase, the voltage from the phase detector causes the VCO output to shift and reduce the phase difference between the input and output. In this manner, the phase detector constantly monitors and adjusts the frequency of the VCO to maintain the phase difference between the input and output at zero. When the phase difference between the two signals is zero, the output is said to be locked.
A PLL is commonly used to stabilize the clock signals, multiply their frequency, synchronize different parts of the circuit, synchronize one chip with another, clean up the signals, and numerous other similar applications. It offers a clean and stable reference signal. The benefits of a PLL depend on many factors, such as how quickly it responds to differences in its phase and adjust its output, what range of input frequencies it handles without losing its locking capabilities, how much noise or jitter exists on the output signal, and the like.
Jitter is a measure of the timing instability in a waveform or circuit. It is the variation from an ideal waveform that is caused by electrical changes, design problems, characteristics of components in a system, or other similar problems. Unexpected changes in frequency, pulse length, and phase are indicative of the presence of jitter. Jitter becomes more significant at higher speeds since the same jitter comprises a larger proportion of the overall signal. Circuits that are time dependent, particularly when they operate at high frequencies, are especially susceptible to problems of jitter.
Microprocessors typically use an on-chip clock signal provided with a PLL. Because multiprocessor systems are commonly used, the timing of events is critical. Conventional systems are configured having a plurality of processors running in parallel, sharing and swapping data and commands to accomplish the computing task. Data is transferred via data busses which are synchronized between the many processors to ensure proper data transfer. Any problem with the data bus results in incorrect data at the other end. Thus, PLL is advantageously used to synchronize different chips attached to the data bus.
As mentioned previously, PLLs are particularly susceptible to jitter. Small amounts of jitter may go unnoticed, but at high speed, jitter on the PLL causes data transfer errors. Redesigning the PLL or the system may normally be an option, but often the problem is not discovered until the system is shipped to a customer when it is no longer feasible to redesign. A way to measure and categorize the jitter is the next best option so that only good chips are used to ensure a good product.
Signal integrity analyzers and other special equipment exist to perform a quick jitter analysis of signals, but this approach is both costly and complicated, especially in a manufacturing environment. Added to the cost of the equipment there is additional time and cost associated to connecting other components to an existing tester, integrating systems, and ensuring proper operation. Preferably, the best approach is to use an existing production logic tester without any additions. It lowers the test cost, reduces the number of necessary components, and allows the use of equipment as it exists